The present invention relates to testing data packet signal transceivers, and in particular, to achieving faster test times by using interleaved device setup and testing.
Many of today's electronic devices use wireless technologies for both connectivity and communications purposes. Because wireless devices transmit and receive electromagnetic energy, and because two or more wireless devices have the potential of interfering with the operations of one another by virtue of their signal frequencies and power spectral densities, these devices and their wireless technologies must adhere to various wireless technology standard specifications.
When designing such wireless devices, engineers take extra care to ensure that such devices will meet or exceed each of their included wireless technology prescribed standard-based specifications. Furthermore, when these devices are later being manufactured in quantity, they are tested to ensure that manufacturing defects will not cause improper operation, including their adherence to the included wireless technology standard-based specifications.
For testing these devices following their manufacture and assembly, current wireless device test systems (also referred to as “testers”) employ a subsystem for analyzing signals received from each device. Such subsystems typically include at least a vector signal generator (VSG) for providing the source signals to be transmitted to the device under test, and a vector signal analyzer (VSA) for analyzing signals produced by the device under test. The production of test signals by the VSG and signal analysis performed by the VSA are generally programmable so as to allow each to be used for testing a variety of devices for adherence to a variety of wireless technology standards with differing frequency ranges, bandwidths and signal modulation characteristics.
As will be readily appreciated, testing of a data packet signal transceiver, also referred to as a device under test (DUT), requires a finite amount of time. Depending upon the wireless technology or standard (and sometimes multiples of which) for which the DUT is to be tested, it will take more or less test time for the DUT to be fully tested to confirm its proper functioning and operation. Times required for these tests have been reduced at times by applying various testing techniques, though further changes in techniques have tended to be insignificant, thereby bringing diminishing returns. As a result, testing techniques have been focused on testing multiple DUTs concurrently so that even though the actual test time per device may not be reduced appreciably, the number of DUTs tested in that time interval increases, thereby having the net effect of reducing overall per-DUT test time, and thereby reducing testing costs for each DUT.
However, when multiple DUTs are to be tested concurrently, using a test system, also referred to as a tester, having a single test signal source (e.g., a single VSG) and a single test signal analyzer (e.g., a single VSA), it is generally not possible to perform a transmit signal test simultaneously for all DUTs. This is due to the fact that the test signal analyzer can only receive, capture and analyze a transmit signal from one DUT at a time. For receive signal testing, where the single test signal source provides a single test signal, it is possible to replicate the test signal using power dividers, and thereby provide simultaneous test signals to multiple DUTs. However, in cases where each DUT has multiple receivers (e.g., multiple-input, multiple-output, also referred to as MIMO), each DUT will still require testing individually, since sourcing the same signal to all DUT receive ports will not allow detection of a bad individual receiver among the DUT receiver circuitry. Thus, each DUT must be controlled between each test sequence. Alternatively, multiple test signal sources can be used to generate multi-stream test signals, but such test signal sources tends to be prohibitively expensive for replicating on the scale needed for manufacturing tests of many DUTs.
In particular, two tasks necessary to perform during DUT testing are those of controlling (e.g., preparing or setting up) the DUT for its upcoming test, and allowing time for the DUT transmitter circuitry to settle to its steady state operation and thereby provide consistent transmit signal power. Both of these tasks must generally be performed at the beginning of a transmit signal test, and can be longer (often significantly) than the duration of the test data packet exchanges between the tester and DUT.
Accordingly, it would be desirable to have a technique for testing data packet signal transceivers in which that time otherwise lost while awaiting initial setup of the DUT for the upcoming test sequence and power settling of its transmitted data packet signal can instead be used for performing useful tasks that are part of, or otherwise associated with, the test to be performed. Additionally, if such testing method could be applied to multiple DUTs for simultaneous testing, further time savings could be achieved.